Conventionally a timing generator employed in a semiconductor testing apparatus has utilized a counter to obtain a desired delay time, and further, an n-phase interleave circuit to produce a delay time up to n-times longer delay than a reference clock period. Furthermore, this counter has achieved a required delay by counting k bits of the reference clock.
FIG. 3 is a block diagram showing an example of a delay circuit configured by counters to be used in the conventional timing generator for a semiconductor testing apparatus. In FIG. 3, first, an n-phase interleave controller 1 is provided to divides a delay trigger signal at its input into n-phases and distributes them to counters. The n-phase interleave controller detects the presence or absence of the delay trigger for each period of the reference clock provided at the other input. If the delay trigger is present, the output of the n-phase interleave controller is advanced by one step. If the output reaches a value n, it goes back to 1 and begins to advance from 1 again.
Counters 11.sub.1 -11.sub.n are provided in a parallel fashion for generating n-phase delay signals. Outputs C1-Cn of the counters 11.sub.1 -11.sub.n are connected to an OR circuit 2. Each counter is provided with delay data and the reference clock. Each counter also has input terminals SA and SB. The input terminal SA receives the delay trigger signal from the n-phase interleave controller 1 and the input terminal SB receives an output signal of the corresponding counter. When the delay trigger signal from the n-phase interleave control 1 exists at the input terminal SA.sub.1 terminal of the counter 11.sub.1, for example, the delay data is loaded in the counter 11.sub.1. The counter 11.sub.1 operates according to the delay data, for example, presets its state to the value indicated in the delay data. The delay data consists of k bits, which is typically on the order of 10 bits.
Initially, the outputs C1-Cn of the counters 11.sub.1 -11.sub.n are Low. Thus, in the counter 11.sub.1, the output C1 is in the low level and supplied to the OR gate 2 and the input terminal S.sub.1. When both input signals at the terminals SA and SB are Low, the counter 11 decrements. That is, whenever the reference clock is supplied, loaded data in the counter will be decremented. If the loaded data reaches 0, the output C and thus the input terminal SB become high, and then the counter 11 is set to a hold mode. The counter 11 maintains the hold mode until receiving the next delay trigger signal from the n-phase interleave controller 1.
FIG. 4 is a timing chart for showing an operation of the delay circuit of FIG. 3. The n-phase interleave controller 1 is given the reference clock and the delay trigger signal as shown in FIGS. 4A and 4B, respectively. The n-phase interleave controller 1 then divides and distributes the delay trigger signal to the terminals SA.sub.1 -SA.sub.n of the counters 11.sub.1 -11.sub.n as shown in FIGS. 4C-4N. The delay data corresponding to the first delay trigger signal at the terminal SA.sub.1 (FIG. 4C) from the n-phase interleave controller 1 is loaded in the counter 11.sub.1.
In the example of FIG. 4, the delay data for the counter 11.sub.1 is "12" (FIG. 4G) and thus the counter 11.sub.1 is set to the value "12". Then the counter 11.sub.1 decrements from 12 by one step for each reference clock of FIG. 4A until it reaches 0 (FIG. 4H). When the counter 11.sub.1 becomes 0, by counting the reference clock 12 times, the output C1 becomes high. Similarly, the delay data corresponding to the second delay trigger at the terminal SA.sub.2 is loaded in the counter 11.sub.2. In this example, delay data indicates "11" (FIG. 4G) so that the counter 11.sub.2 is set to "11". The counter 11.sub.2 decrements from 11 to 0 by the timing of the reference clock interval. The output C2 of the counter 11.sub.2 becomes high after counting the reference clock 11 times (FIG. 4I).
In the similar manner, the delay data corresponding to the third delay trigger at the terminal SA.sub.3 is loaded in the counter 11.sub.3. The delay data for the counter 11.sub.3 indicates "9" (FIG. 4G) so that the counter 11.sub.2 is set to "9". The counter 11.sub.3 decrements from 9 to 0 step by step for each reference clock of FIG. 4A. The output C2 of the counter 113 becomes high after counting the reference clock 9 times (FIG. 4I). The outputs C1-Cn shown in FIGS. 4L-4O are coupled by the OR circuit 2 which generates the timing signal of FIG. 4P whose delay time is controlled by factors k and n of the reference clock.
The example of FIGS. 3 and 4 show only a part of the circuit configuration for one test pin for a IC device to be tested. For example, this circuit determines a timing (an edge) when a test signal for the IC device under test changes its state. In the semiconductor testing apparatus, each test pin requires several kinds of timing edges for generating complex test signals. That is, even for one test pin in the semiconductor testing apparatus, more than four or five circuits shown in FIG. 3 must be installed. The semiconductor testing apparatus is required to have the number of test pins equal to or greater than the number of an IC device pins.
Since some of the recent IC devices have device pins as many as several hundreds, the total number of delay circuits shown in FIG. 3 required in the semiconductor testing apparatus becomes extremely large. Especially, as the delay data k increases, the circuit size increases. Moreover, as the number of interleave phase n increases, the circuit scale further increases.
Therefore, the conventional timing generator for use in the semiconductor testing apparatus has the following disadvantages. The circuit size of the delay circuit increases with the increase of the number of interleave phase n, since the number of counters equal to n has to be installed in the delay circuit. In addition, the circuit size has to be increased corresponding to the increase in the number of device pins of IC device to be tested. Thus, the circuit structure in the conventional timing generator requires a large amount of hardware in the semiconductor testing apparatus and as a consequence increases the cost of the testing apparatus.